Staff Engineer, Design Verification Engineer
Core
Senior Design Verification Engineer responsible for owning testbench architecture, developing UVM-based verification infrastructure, and verifying key digital IP blocks within mixed-signal devices for the consumer audio market.
Role type
Senior IC Design Verification Engineer
Builds
Mixed-signal SoCs and digital IP blocks for portable, wearable, and gaming audio solutions
Domain
Semiconductor / Analog & Mixed-Signal / Consumer Electronics
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM methodology, SystemVerilog, Verilog, functional coverage closure, code coverage analysis, assertion development, IP and SoC level verification, scripting (Python, Perl, Makefile), post-silicon bring-up support
Preferred skills
AHB/AXI/APB protocols, power-aware simulation, formal verification, DSP concepts, audio IP verification
Technologies
UVM, SystemVerilog, Verilog, Python, Perl, Makefile, AHB, AXI, APB
Responsibilities
Develop testbench architecture and testplans; verify key digital IP blocks in mixed-signal devices; debug gating issues and articulate findings to engineering leads; integrate block-level testbenches at SoC top-level; improve verification coverage and reduce verification time; support post-silicon activities including silicon bring-up and ATE pattern bring-up
Seniority
Senior, hands-on IC
