Staff Engineer, Design verification
Core
Verify complex mixed/digital signals ICs, including digital signal processing data-paths, high-speed interfaces, and sub-system controllers for Data Center Power Conversion solutions.
Role type
Staff Design Verification Engineer
Builds
Power Conversion ICs for Data Centers
Domain
Semiconductor / Analog & Digital IC Design
Deliverable
production ML models | product features
Required skills
System Verilog, UVM, constrained random functional verification, functional coverage, assertions, formal verification, gate-level simulation, debugging, Perl/Python scripting, test plan development
Preferred skills
PMBus, SPI, OTP/MTP, I2C protocols, mentoring junior engineers
Technologies
System Verilog, UVM, Perl, Python
Responsibilities
Develop verification plans and environments from scratch; verify blocks and sub-systems using leading-edge methodologies; own complex feature verification; mentor junior engineers; improve verification flow and methodology; perform gate-level simulations and debugging.
Seniority
Senior, hands-on IC