Senior Physical verification
Core
Lead block-level digital design synthesis and static timing analysis (STA) to achieve timing closure and power optimization for complex SoC designs.
Role type
Senior Digital Design Engineer (Synthesis & STA)
Builds
High-speed SoC designs in cutting-edge process technologies (16nm and below)
Domain
Semiconductor / Digital IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure
Required skills
Digital Synthesis, Static Timing Analysis (STA), Timing Constraints Development, Power Optimization, Timing ECOs, DFT/Scan insertion, RTL-to-GDS flow knowledge, Tcl/Perl/Python scripting, Root cause analysis of timing violations
Preferred skills
Floor-planning, Placement, CTS, Routing, Physical Verification, EM/IR flows, Signoff checks
Technologies
Synthesis tools, STA tools, LEC, PD tools, Physical design tools
Responsibilities
Develop timing constraints for complex blocks, achieve timing closure on complex designs, optimize digital designs for power efficiency, troubleshoot timing violations across design implementation stages, automate timing analysis tools using scripts, perform or oversee physical design tasks (floor-planning, placement, routing) and signoff checks
Seniority
Senior, hands-on IC
