Manager, Design Verification
Core
Lead physical design implementation for complex block- and top-level SoCs, ensuring timing closure, power integrity, and signoff quality while leading a small engineering team.
Role type
Senior IC physical design engineer (technical lead)
Builds
Advanced-node SoCs (22nm to 4nm) for semiconductor solutions
Domain
Semiconductor / Physical Design / Digital SoC
Deliverable
production ML models | product features | infrastructure
Required skills
End-to-end physical design (floorplanning, power planning, placement, CTS, routing, ECO), Timing closure, IR/EM analysis, Signal integrity, Physical verification (DRC/LVS), Hierarchical PNR strategies, EDA tool automation, Team leadership and mentoring
Preferred skills
Experience with advanced nodes (5nm/4nm), Cross-functional collaboration with RTL/DFT/CAD teams, Debugging complex tool issues
Technologies
Cadence Innovus, Synopsys ICC2, Tempus, PrimeTime, RedHawk, Voltus
Responsibilities
Own end-to-end physical implementation for complex blocks or subsystems; Drive timing closure, congestion resolution, and signoff; Develop and maintain physical design methodologies and automation scripts; Provide technical direction and mentor junior engineers; Collaborate with RTL, STA, DFT, and packaging teams to converge on implementation-friendly architectures
Seniority
Senior, hands-on IC with technical leadership