Manager, Design Verification
Core
Lead physical design implementation for complex block- and top-level SoCs on advanced nodes, leading a small team to deliver high-quality, on-time results.
Role type
Senior IC physical design engineer (technical lead)
Builds
Complex digital SoCs for the Intelligent Edge (analog, digital, AI, software solutions)
Domain
Semiconductor / Physical Design / Advanced Node SoC
Required skills
Physical design implementation (floorplanning, power planning, placement, CTS, routing, ECO), Timing closure, IR/EM analysis, Signal integrity, Physical verification (DRC/LVS/antenna), Hierarchical PNR strategies, IO ring/PG structures, EDA tool debugging, Scripting and flow automation, Team leadership and mentoring
Preferred skills
Experience with advanced nodes (22nm, 16nm, 7nm, 5nm, 4nm), Cross-functional collaboration with RTL/STA/DFT teams
Technologies
Cadence Innovus, Synopsys ICC2, Tempus/PrimeTime, RedHawk, Voltus
Responsibilities
Own end-to-end physical implementation for complex blocks or subsystems, Drive timing closure and congestion resolution, Define hierarchical PNR strategies and integration guidelines, Develop and maintain physical design methodologies and automation scripts, Provide technical direction and mentorship to a small group of engineers, Collaborate with RTL, STA, DFT, and packaging teams
Seniority
Senior, hands-on IC with technical leadership
