HW I/P Lab Lead
Core
Lead a team in the architecture, design, and validation of next-generation purpose-specific custom hardware IP blocks.
Role type
Senior IC Hardware IP Design and Verification Lead
Builds
Custom hardware IP blocks for product differentiation
Domain
Semiconductor / Hardware IP / Digital Design
Deliverable
production ML models | product features
Required skills
RTL Design, Design Verification, System Verilog, UVM/OVM, FPGA Prototyping, ASIC Validation, Low Power Implementation, Timing Analysis, Clock Domain Crossing, Sub-system Integration (PCIe, USB, DDR, ARM/RISC-V, MIPI), Python, C, SystemC
Preferred skills
AI Tool usage for IP development, NPU subsystem knowledge, Multimedia/Display/Camera subsystem expertise
Technologies
System Verilog, UVM, OVM, Verilog, FPGA, ASIC, UPF, CPF, ARM, RISC-V, PCIe, USB, DDR, MIPI, NPU
Responsibilities
Manage and mentor a multi-disciplinary team of RTL Design and Design Verification Engineers, Oversee the end-to-end IP lifecycle including micro-architecture definition and RTL coding, Ensure robust validation methods to achieve zero-bug silicon, Define and implement best-in-class engineering practices and design flows
Seniority
Senior, hands-on IC with people leadership
