RTL Design Lead
Core
Lead RTL design and verification for complex chips, SoCs, and IP blocks, guiding microarchitecture from conception to tape-out.
Role type
Senior IC RTL Design Lead
Builds
Complex chips, System-on-Chips (SoCs), and IP/Sub-system blocks
Domain
Semiconductor hardware design
Required skills
Verilog, System-Verilog, Python, Perl, ARM architecture, RISC-V, AXI/AHB protocols, PCIe, USB, DDR, Static Timing Analysis (STA), Clock Domain Crossing (CDC), Logical Equivalence Checking (LEC)
Technologies
Verilog, System-Verilog, Python, Perl, ARM, RISC-V, AXI, AHB, PCIe, USB, DDR
Responsibilities
Drive end-to-end design development of IP/Sub-system blocks and SoCs to meet PPA targets; Manage, mentor, and set goals for a team of digital engineers; Oversee design reviews to optimize Power, Performance, and Area (PPA) metrics; Partner with architecture, verification, and physical design teams; Drive resolution on complex bugs, logic issues, and sign-off checks.
Seniority
Senior, hands-on IC
