SRAM Layout Engineer
Core
Developing SRAM memory layouts and performing physical verification for complex semiconductor designs in advanced CMOS processes.
Role type
Senior IC layout engineer (SRAM)
Builds
SRAM memory blocks for System LSI and Memory products
Domain
Semiconductor / VLSI Design
Deliverable
production ML models | product features | infrastructure
Required skills
SRAM layout development, physical verification, layout area and routing optimization, design rule compliance, yield and reliability analysis, electro-migration analysis, latch-up analysis, coupling and crosstalk analysis, IR-drop analysis, parasitic analysis, matching, shielding, schematic understanding
Preferred skills
Interface with circuit designers and CAD teams, understanding layout effects on circuit speed, capacitance, power, and area
Technologies
Advanced CMOS process
Responsibilities
Perform SRAM memory layout development, execute physical verification activities, optimize layout area and routing, analyze yield and reliability issues, evaluate layout effects on circuit performance metrics
Seniority
Senior, hands-on IC
