Design Verification Engineer, Coherent Interconnect
Core
Design Verification Engineer for System IP, specifically coherent interconnects and caches, ensuring high-performance, low-latency solutions for complex SoC designs.
Role type
Senior IC Design Verification Engineer
Builds
Reusable verification environments, testbenches, and verification strategies for coherent interconnect IPs.
Domain
Semiconductor / SoC Architecture / Coherent Interconnects
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, testbench architecture, covergroups, assertions, checkers, Git, Unix/Perl scripting, ARM protocols (CHI, AXI, ACElite, APB), coverage analysis, debugging functional failures
Preferred skills
LPDDR memory controller verification, formal verification, power-aware verification (UPF), gate-level simulation
Technologies
SystemVerilog, UVM, Git, Unix, Perl, ARM CHI, AXI, ACElite, APB
Responsibilities
Develop and maintain expertise in microarchitecture and design verification for coherent interconnect IPs; architect and develop reusable verification environments and testbenches from scratch; execute verification strategy and support project goals; define new verification methodologies and improve flows; collaborate with design and SoC teams to analyze and debug failures.
Seniority
Senior, hands-on IC
