Senior DFT Design Engineer
Core
Design and implement DFT architectures, test logic insertion, and validation flows for complex ICs including FPGAs, processors, DSPs, and multi-die packages.
Role type
Senior IC DFT Design Engineer
Builds
FPGA, processor, DSP, SERDES, IO, and 2.5D/3D multi-die IC designs
Domain
Semiconductor IC Design / Digital Logic
Required skills
DFT architecture definition, test logic insertion, ATPG pattern generation, RTL and gate-level design, EDA tool proficiency (synthesis, scan, simulation, STA), scripting (Perl/TCL), pre-silicon validation
Preferred skills
Test compression, BIST (MBIST/LBIST), advanced fault models, 2.5D/3D multi-die design experience, high-speed IO/SerDes DFT
Technologies
Perl, TCL, ATPG tools, Synthesis tools, Scan insertion tools, Simulation tools, STA tools
Responsibilities
Define and implement DFT architectures and specifications; Perform test logic insertion and ATPG; Collaborate with IP and integration teams; Partner with test development for silicon bring-up and debug; Contribute to DFT methodology and automation flows; Ensure manufacturability goals (coverage, cost, yield)
Seniority
Senior, hands-on IC
