Physical Design Implementation and Signoff Methodology Lead & Architect
Core
Architect and own the end-to-end physical design implementation and signoff methodology (place-and-route, EMIR, timing, power) across Altera's FPGA product portfolio, integrating AI/ML techniques to improve closure speed and quality.
Role type
Senior Principal Engineer (Individual Contributor)
Builds
Scalable, AI/ML-enhanced physical design flows and signoff standards for advanced process nodes
Domain
Semiconductor / FPGA Physical Design / EDA
Deliverable
production ML models | product features
Required skills
Physical design implementation and signoff methodology, Electromigration and IR-drop (EMIR) analysis, Static Timing Analysis (STA), Power signoff, Place-and-route, AI/ML for EDA optimization, Advanced process node expertise, EDA tool proficiency
Preferred skills
Mentorship of design and CAD engineers, Cross-functional technical leadership, Qualification of next-generation methodologies
Technologies
Ansys RedHawk-SC, Synopsys PrimeTime/PrimePower/Fusion Compiler, Cadence Innovus/Voltus/Tempus
Responsibilities
Define and improve PD implementation/signoff flows and standards, Champion AI/ML-driven productivity in signoff, Architect flows for scalable closure across concurrent designs, Partner with process/EDA teams on technology enablement, Establish quality gates and golden reference flows, Lead root-cause analysis of complex signoff issues, Mentor engineers on best practices
Seniority
Senior Principal Engineer, hands-on IC