Physical Design Lead — Execution
Core
Drive day-to-day physical design execution and delivery for FPGA chips from floorplan through tapeout, ensuring schedule and quality closure for blocks and full-chip integration.
Role type
Senior Individual Contributor (Principal/Sr. Principal) Physical Design Lead
Builds
Programmable logic and adaptive computing solutions (FPGAs) for data centers, networking, automotive, aerospace, and industrial applications.
Domain
Semiconductor / FPGA Physical Design / Advanced Node IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> production ML models (Incorrect mapping in thought, correcting to: production hardware chips / silicon)
Required skills
Physical design execution (floorplan, placement, CTS, routing, timing/power closure), Advanced node tapeout ownership (7nm/5nm/3nm/18A), Signoff flows (STA, EMIR, physical verification, formal equivalence), Scripting (Python/Tcl/Perl/Shell), Cross-block coordination, Customer technical engagement, Risk mitigation under pressure
Preferred skills
Full-chip implementation ownership, Customer-facing technical reviews, PD signoff methodology partnership, Informal team leadership
Technologies
Synopsys Fusion Compiler/ICC2/PrimeTime, Cadence Innovus/Tempus/Voltus, Ansys RedHawk-SC, Siemens Calibre
Responsibilities
Drive physical design execution and delivery across blocks and full-chip integration; Own schedule and quality bar, proactively identifying and mitigating risks; Coordinate execution across multiple design teams to resolve conflicts; Engage senior customer technical stakeholders directly; Serve as escalation point for execution blockers; Mentor physical design engineers on execution best practices
Seniority
Senior, hands-on IC (Principal/Sr. Principal level)