Senior ASIC Verification Engineer, onsite Kanata
Core
Verify functional blocks and subsystems for Ciena's Wavelogic optical fiber transmission products using simulation, formal, and coverage methods.
Role type
Senior IC ASIC verification engineer
Builds
Verified functional blocks and subsystems for optical fiber transmission solutions
Domain
Telecommunications / Optical networking
Required skills
System Verilog UVM, C, formal verification, coverage driven verification, OTN/B100G/Ethernet protocols, Python, C++, System C
Preferred skills
None stated
Technologies
System Verilog UVM, C, Python, Make, bash, System C
Responsibilities
Propose and implement innovative verification strategies; build verification test plans and testbench environments; perform coverage driven verification and monitor regressions; debug failures with designers; report status updates
Seniority
Senior, hands-on IC
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