Sr Staff Digital Verfication Engineer
Core
Designing and developing verification environments for semiconductor designs, improving verification architecture and flow, and running simulations to ensure functionality.
Role type
Sr Staff Digital Verification Engineer
Builds
Verification environments and testbenches for embedded semiconductor solutions
Domain
Semiconductor / Hardware Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System Verilog, UVM, RTL simulation, gate-level simulation, code coverage development, test plan creation, assertion writing, debugging designs, computer architecture knowledge
Preferred skills
Python scripting, C/C++/Java, software design patterns, DDR protocol knowledge, mixed-signal verification experience, experience with 100K+ lines of verification environment
Technologies
System Verilog, UVM, Python, C/C++, Java
Responsibilities
Understanding expected functionality of designs, designing and developing verification environments, improving verification architecture and flow, running RTL and gate-level simulations/regression, code/functional coverage development, analysis and closure
Seniority
Sr Staff, hands-on IC
