FPGA IP Software Development Engineer
Core
Architect, develop, and productize parameterizable FPGA Soft IP cores for release via Quartus and Platform Designer, owning the lifecycle from micro-architecture to customer-ready delivery.
Role type
Senior IC FPGA Soft IP Design Engineer
Builds
Reusable, high-performance FPGA Soft IP cores (RTL) for external customers
Domain
Semiconductor / FPGA Design & Verification
Deliverable
production ML models
Required skills
FPGA Soft IP design, RTL (Verilog/SystemVerilog/VHDL), IP packaging (Quartus/Qsys), Static Timing Analysis (STA), Clock Domain Crossing (CDC), synthesis, functional simulation, debug, technical leadership
Preferred skills
High-speed interface IP (JESD204B/C, Ethernet), PCIe/DDR/CPRI, UVM, functional coverage, Python/Tcl/Perl scripting
Technologies
Quartus, Platform Designer (Qsys), Verilog, SystemVerilog, VHDL, Git, Python, Tcl, Perl, AXI, Avalon
Responsibilities
Architect and implement parameterizable RTL; own IP lifecycle (synthesis, simulation, lint, CDC, STA); package IP for Quartus catalog; define register maps and interfaces; design simulation testbenches and regression suites; debug IP issues across simulation and hardware; mentor junior engineers
Seniority
Senior, hands-on IC with mentorship responsibilities
