IP Logic Design Engineer
Core
Lead FPGA design and platform enablement for Altera development kits, spanning architecture definition, RTL implementation, timing closure, and board bring-up.
Role type
Senior IC FPGA RTL Design Engineer
Builds
FPGA development kits and platform enablement solutions
Domain
Semiconductor / FPGA Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> product features (FPGA designs)
Required skills
Verilog, SystemVerilog, Quartus Prime flow, digital design fundamentals (FSMs, pipelining, CDC), board bring-up and debugging, high-speed interface protocols (PCIe, Ethernet, DDR, JESD), simulation and verification (Questa, ModelSim, assertions), technical leadership and mentoring
Preferred skills
Python, Tcl, Linux environments, schematic reading, hardware debugging tools (oscilloscopes, logic analyzers, JTAG)
Technologies
Quartus Prime, Questa, ModelSim, PCIe, Ethernet, DDR4/DDR5, JESD, AMBA AXI, Avalon-MM, Signal Tap
Responsibilities
Define FPGA architecture and microarchitecture; design and maintain synthesizable RTL; translate system requirements into RTL features; own FPGA development flow including synthesis and timing closure; support board bring-up and validation; create RTL testbenches and simulation environments; lead technical reviews and mentor engineers; collaborate with board and IP teams to debug system issues
Seniority
Senior, hands-on IC
