Senior FPGA IP Design Engineer
Core
Designing high-performance, parameterizable soft IP blocks (e.g., AMBA AXI Interconnect) for FPGA architectures.
Role type
Senior IC FPGA Soft IP Design Engineer
Builds
System-level IP cores for FPGA platforms
Domain
Semiconductor / FPGA Design
Required skills
RTL design, AMBA AXI4 protocol, FPGA implementation tools, EDA simulation, Python/Tcl/Perl scripting, CDC/RDC analysis
Preferred skills
Micro-architecture definition, timing closure, verification collaboration
Technologies
Siemens Questa/Modelsim, Synopsys VCS
Responsibilities
Define micro-architecture and develop RTL for critical blocks (schedulers, pipelines, coherency logic); collaborate with verification on test plans and debug; resolve timing/power/congestion with physical design team; provide technical support for pre-sales and post-sales engagements; mentor junior engineers
Seniority
Senior, hands-on IC
