Principal Digital Verification Engineer
Core
Expert digital verification engineer responsible for simulating and validating functional blocks, cores, and subsystems for Ciena's Wavelogic optical fiber transmission products.
Role type
Principal ASIC verification engineer (Serdes focus)
Builds
Digital verification strategies and validation for Serdes and Wavelogic optical transmission products
Domain
Telecommunications / Optical fiber transmission / Digital ASIC design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System Verilog, UVM, SVA, formal verification methods, simulation environment design, test case creation, functional coverage analysis, schedule estimation, technical problem debugging
Preferred skills
Python, C, C++, Make, bash, Jira, GIT, DSP, Forward Error Correction
Technologies
System Verilog, UVM, SVA, Jira, GIT, Python, C, C++, Make, bash
Responsibilities
Propose and implement innovative verification strategies; validate entire subsystems using simulation, formal, and coverage methods; create and optimize simulation environments and test plans; lead focused groups or mentor individuals; estimate and track project schedules; participate in architectural and design reviews to advise on verification impacts
Seniority
Principal, hands-on IC with mentorship responsibilities
