Senior Manager, Layout Design
Core
Lead design enablement and implementation of best-in-class high-speed analog layouts for advanced CMOS and BiCMOS technologies, including SERDES, optical-line-facing circuits, and precision analog macros.
Role type
Senior Manager, Analog Layout Design
Builds
High-speed analog circuits (DAC/ADC, modulator drivers, TIA) for 112G/224G connectivity solutions
Domain
Semiconductor manufacturing / High-speed analog IC design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog high-speed layout design, Floor-planning, Physical verification, Electromigration checks, PERC verification, Scripting (pcells), Template-based methodology, Calibre/ICV debugging, Advanced analog design tools (Cadence Virtuoso, Mentor, Synopsys)
Preferred skills
Managing MPWs/test chips, Deep-submicron process knowledge, Cross-timezone collaboration
Technologies
Cadence Virtuoso, Calibre, ICV, Synopsys, Mentor Graphics
Responsibilities
Lead Block and Macro level layout development including floor-planning and optimization, Plan and schedule projects for successful delivery, Perform feasibility work with circuit topologies, Undertake physical verification and electromigration checks, Automate layout flows with scripts, Mentor junior team members
Seniority
Senior Manager, hands-on IC leadership
