Lead RF Layout Designer
Core
Leading the physical implementation of high-performance RF/analog integrated devices, test structures, and supporting technology development and PDK enablement.
Role type
Lead RF Layout Designer (Senior IC)
Builds
RF/Analog integrated devices, test structures, and qualification test chips
Domain
Semiconductor manufacturing, RF/Analog CMOS technologies
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RF/Analog layout design, CMOS technologies, Cadence Virtuoso, SKILL programming, foundry design rules, layout optimization, complex layout delivery, independent problem solving, cross-functional collaboration
Preferred skills
Advanced node technology development, RF communication applications, design compacting and optimization, technical project leadership, PDK development, design rule definition
Technologies
Cadence Virtuoso, SKILL
Responsibilities
Lead layout design and physical implementation for RF/Analog circuits and test structures; Deliver qualification test chips on schedule while meeting quality and cost targets; Collaborate with device, process, and design teams to define and validate design rules and methodologies; Support new technology node enablement, stack development, and layout guidelines; Provide feedback for improving PDK quality, design rules, and layout productivity; Develop and utilize automation scripts to enhance design efficiency; Optimize layouts for performance, area, and manufacturability while adhering to foundry rules; Lead small teams or projects, acting as a technical/project leader when required; Train and mentor junior engineers to improve workflow quality and technical capability
Seniority
Senior, hands-on IC with technical leadership
