DFX Verification Engineer
Core
Sr. SoC Design Verification Engineer focused on Design for Debug architecture verification, creating test cases and test benches using UVM methodology for pre-silicon system verification.
Role type
Senior IC SoC Design Verification Engineer
Builds
Pre-silicon SoC, FPGA, and Full Chip designs
Domain
Semiconductor / ASIC Design Verification
Required skills
UVM methodology, System Verilog, Formal verification, Design for Debug (JTAG, USB, PCIe), Full chip/system functional verification, Emulation
Preferred skills
ARM and RISC Debug Architectures, UltraSoC/Tessent Embedded Analytics Debug Architecture, Perl, Python, Linux/Unix scripting (via careerplan.io/jobs/R02797-dfx-verification-engineer-at-altera)
Technologies
UVM, System Verilog, JTAG, High speed USB, PCIe, FPGA, Emulation
Responsibilities
Create testcases and testbench with UVM methodology; Define verification strategies/methodology and test plan for fullchip/system functional verification; Coordinate cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan; Perform pre-silicon system verification including SoC, FPGA & Full Chip design verification.
Seniority
Senior, hands-on IC
