Staff Engineer
Core
Multi-skilled RTL and Verification engineer specializing in DFT for complex memory and IO subsystems.
Role type
Staff Engineer, IC Design (RTL/Verification/DFT)
Builds
Digital subsystems, Memory Subsystems including BIST, Hierarchical Blocks
Domain
Semiconductor, Digital IC Design
Deliverable
production ML models | product features
Required skills
RTL development, Verification (OVM, UVM), DFT flows (MBIST, ATPG, RSQ), Formal verification, Cross Clock Domain checks, Timing closure, Synthesis constraints, Verilog NC/XL
Preferred skills
Spyglass, LEC, CDC, Synthesis tools (DC Ultra, Fusion Compiler), GLS, Simulation
Technologies
Verilog, OVM, UVM, MBIST, ATPG, RSQ, Spyglass, LEC, DC Ultra, Fusion Compiler
Responsibilities
Develop and verify RTL for digital and memory subsystems; Implement DFT flows including MBIST, ATPG, and RSQ; Perform formal verification and cross-clock domain checks; Ensure power and timing sign-off; Create independent verification suites using OVM/UVM methodologies.
Seniority
Staff, hands-on IC
