Emulation Engineer
Core
Pre-silicon verification of networking ASICs using emulation platforms to define test plans and verify chip architecture.
Role type
Junior IC emulation engineer (ASIC verification)
Builds
Networking switch chips (ASICs) for high-density, high-bandwidth applications
Domain
Semiconductors / Networking ASICs
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Verilog/SystemVerilog, C/C++, Tcl, Python, emulation platforms (Zebu/Palladium), debugging, coverage-driven verification
Preferred skills
Pre-silicon verification experience, traffic generators (IXIA/Spirent), high-speed interface protocols (PCIe/Ethernet), DPI transactors, assertions
Technologies
Zebu, Palladium, Tcl, ITcl, Python, C/C++, Verilog, SystemVerilog
Responsibilities
Develop sub-system and chip-level tests using scripting languages; Contribute to building synthesizable Verilog/SystemVerilog models for emulation; Participate in block, sub-system, and chip/system-level debugging; Write and maintain automation scripts for emulation methodologies; Collaborate with Architecture, Design, and DV teams for verification coverage
Seniority
Junior, 0-2 years experience
