DFT Engineer
Core
DFT Engineer responsible for ATPG and MBIST pattern generation, debug, and yield enhancement for networking switches in AI and traditional data centers.
Role type
Senior IC DFT Engineer
Builds
Networking switches for Scale up and Scale Out data centers
Domain
Semiconductor manufacturing / Digital Logic Testing
Deliverable
production ML models | product features | dashboards & analysis
Required skills
CMOS device physics, semiconductor manufacturing processes (Lithography, Etch, Deposition, CMP, Implant), Testability techniques (SCAN, MBIST, bscan), ATPG pattern generation, Mentor/Siemens DFT Tessent tools, Post Silicon debugging, Data analysis scripting, AI tools for automation
Preferred skills
Strong scripting, AI tools for quick script development
Technologies
Mentor/Siemens DFT Tessent, AI tools
Responsibilities
Generate and debug ATPG/MBIST DFT patterns for post-silicon support; Monitor wafer sort and final test yield to drive continuous improvement; Perform scan diagnostic and repair debug for root cause analysis; Support physical failure analysis and electrical fault isolation; Partner with Global Operations for NPI and silicon bring-up; Build automated dashboards and yield correlation models using AI tools.
Seniority
Senior, hands-on IC
