ASIC VERIFICATION ENGINEER
Core
Develop and maintain verification environments for cutting-edge CSG Switches and AI Network Infrastructure using SystemVerilog/UVM.
Role type
Senior IC ASIC verification engineer
Builds
Chip-level verification environments and test plans for network switches
Domain
Semiconductor / Network Infrastructure
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM methodology, Chip-level (SoC) verification, Coverage Driven Methodology, Gate Level Simulations, Co-Simulation (HW/SW) flow, Simulation tools (VCS), Waveform debug (Verdi), Formal tools (Jasper), Test Bench Accelerators/Emulation Platforms
Preferred skills
Scripting languages (Perl, Python, SED/Awk), Networking protocols (L2/L3/L4, 1588TS, UEC), High Speed bus protocols (PCIe, Ethernet, AXI4.0), Chip level Interconnect/Testability Functions (JTAG, I2C, PLLs), ATE
Technologies
VCS, Verdi, Jasper, UVM, SystemVerilog
Responsibilities
Develop and maintain verification environments in SV/UVM, Collaborate with Arch/uArch/Design teams for test plan development, Execute coverage closures and gate level simulations, Debug co-simulations (HW/SW)
Seniority
Senior, hands-on IC
