ASIC VERIFICATION ENGINEER
Core
Develop and maintain verification environments for cutting-edge CSG Switches and AI Network Infrastructure using SystemVerilog/UVM.
Role type
Senior IC ASIC verification engineer
Builds
Chip-level verification environments and test plans for network switches
Domain
Semiconductor / Network Infrastructure
Required skills
SystemVerilog, UVM, Chip-level SoC verification, Coverage Driven Methodology, GLS, ATE, Co-Simulation (HW/SW), Perl/Python/SED/Awk scripting, Simulation tools (VCS, Verdi), Formal tools (Jasper)
Preferred skills
Networking protocols (L2/L3/L4, 1588TS, UEC), High-speed bus protocols (PCIe, Ethernet, AXI4.0), Chip-level Interconnect/Testability (JTAG, I2C, PLLs), Test Bench Accelerators/Emulation Platforms
Technologies
SystemVerilog, UVM, VCS, Verdi, Jasper, Perl, Python, SED, Awk
Responsibilities
Develop and maintain verification environments in SV/UVM, Work with Arch/uArch/Design teams on test plan development, Execute coverage closures and gate-level simulations, Debug co-simulations (HW/SW)
Seniority
Senior, hands-on IC
