Design Verification Engineer
Core
Define verification plans and environment architecture, develop test cases and bench components, perform coverage analysis/closure, and debug complex digital and mixed-signal IP blocks for Broadcom ASICs.
Role type
Senior IC design verification engineer (digital/mixed-signal)
Builds
Complex custom ASICs and embedded IP blocks
Domain
Semiconductor / ASIC Design / Digital & Mixed-Signal Circuits
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> production verification environments and testbenches
Required skills
SystemVerilog, UVM, SystemVerilog Assertions (SVA), RTL design, gate-level netlist analysis, SDF analysis, Perl/Python/Tcl scripting, version control (git/DesignSync), coverage analysis, random/directed test generation, analog circuit debugging (PLL/DLL/ADC/DAC)
Preferred skills
Emulation platforms (Palladium/Veloce/Zebu), FPGA prototyping (Xilinx), formal verification, iJTAG verification (ICL/PDL/Tessent), co-simulation
Technologies
SystemVerilog, UVM, SVA, Perl, Python, Tcl, Synopsys, Cadence, Mentor, DesignSync, git, Xilinx, Palladium, Veloce, Zebu, Tessent
Responsibilities
Define verification plans and environment architecture; develop test cases, agents, checkers, and behavioral models; analyze and debug simulation failures at RTL and gate-level; achieve coverage goals; collaborate with design teams and EDA vendors; lead adoption of advanced verification methodologies
Seniority
Senior, hands-on IC
