High Speed Analog I/O designer
Core
Design and optimize high-speed interface buffer chips for DDR/LP5/5X/6, chiplets, and beyond in FinFET process nodes.
Role type
Senior IC analog hardware engineer (high-speed I/O)
Builds
High-performance interface buffer chips for memory and chiplet applications
Domain
Semiconductor / High-speed analog I/O
Deliverable
production ML models | product features
Required skills
High-speed DDR I/O design, Chip-chip interface design, Analog receiver circuit design (CTLE, DFE, slicers), Transmitter circuit design (FIR filter, slew rate control), FinFET technology expertise, Analog layout and parasitic management, Signal integrity analysis, Power management, Custom digital design (Serializer/Deserializer), Analog simulation (Cadence Virtuoso, Spectre, HSPICE)
Preferred skills
Design for reliability (EM, IR, aging), Industry standards knowledge for DDR/chiplet I/O
Technologies
Cadence Virtuoso, Maestro, Spectre, HSPICE
Responsibilities
Design and optimize high-speed DDR circuits and chiplet I/Os, Develop circuit architectures to address performance bottlenecks, Oversee physical layout to minimize parasitics, Analyze customer silicon data for design enhancement, Conduct simulations to validate design performance and reliability
Seniority
Senior, hands-on IC