Subsystem/SoC Level Verification Engineer
Core
Develop and maintain functional verification environments for Ethernet Subsystem and SoC designs using System Verilog and UVM.
Role type
Senior IC verification engineer (Ethernet Subsystem/SoC)
Builds
Production-ready verification environments, block/system level test plans, and debug solutions for Ethernet IP.
Domain
Semiconductor hardware verification, Ethernet (MAC, PCS, SerDes)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System Verilog, UVM, BFM development, Checkers, Monitors, Scoreboards, Block/System level verification planning, Debugging test failures, Functional coverage, Constrained random verification, Perl scripting, Tcl scripting, Gate-level/SDF simulation
Preferred skills
Experience with Cadence or Synopsys CAD tools
Responsibilities
Develop verification environments using System Verilog and UVM; Create and execute block/system level verification plans and tests; Debug test failures to identify root causes; Manage functional coverage; Perform gate-level and SDF simulations.
Seniority
Senior, hands-on IC
