Design Verification Engineer
Core
Lead and execute comprehensive verification strategies for next-generation silicon SoC designs at block and system levels.
Role type
Lead/Principal ASIC Design Verification Engineer
Builds
Robust, scalable, object-oriented verification environments and testbenches for advanced node technologies
Domain
Semiconductor / ASIC Design Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (verification environments)
Required skills
SystemVerilog, UVM, C/C++, Perl, Python, Tcl, RTL verification methodologies, block-level verification, system-level verification, advanced process node technologies (5nm and below)
Preferred skills
Hardware design, hardware debugging, SystemC, hardware emulation (Palladium, Zebu), FPGA-based prototyping, EDA tools, front-to-back silicon development lifecycles
Technologies
SystemVerilog, UVM, C, C++, Perl, Python, Tcl, Palladium, Zebu
Responsibilities
Define and deploy advanced ASIC design verification flows and DV methodologies, independently debug complex design and verification issues, partner with design teams to ensure alignment on coverage and architectural goals
Seniority
Senior, hands-on IC with leadership responsibilities
