ASIC Physical Design Engineer
Core
Develop state-of-the-art IC solutions using Broadcom's leading-edge CMOS cell-based ASIC technologies through the full development lifecycle.
Role type
Senior IC Design Engineer (ASIC Physical Design)
Builds
28nm/16FF ASIC chips
Domain
Semiconductor / VLSI / ASIC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Full chip synthesis flow (DC, DCT, DCG), Static Timing Analysis (STA), Floor planning, Placement, Design closure, DRC & LVS, RTL analysis, Design optimization, Timing verification, Simulation, Test insertion, Vector generation, Post-prototype test support, Perl/Tcl scripting
Preferred skills
DFT insertion, Power/IVD analysis, Tapeout experience in 28nm and beyond
Technologies
28nm, 16FF, 16nm, 7nm, CMOS, DC, DCT, DCG
Responsibilities
Perform full chip synthesis and static timing analysis; Execute physical design implementation including floor planning, placement, and design closure; Conduct DRC and LVS checks; Handle block implementation and top-level tasks independently; Support RTL analysis, design optimization, and simulation; Provide post-prototype test support.
Seniority
Senior, hands-on IC