R&D Engineer Physical Design
Core
Physical design engineer responsible for taking integrated circuit designs from concept to product release, focusing on CMOS ASICs for AI/ML, wireless, networking, computing, and storage applications.
Role type
Senior IC physical design engineer
Builds
Production CMOS ASICs for AI/ML, wireless, networking, computing, and storage applications
Domain
Semiconductor / Physical Design
Deliverable
production ML models | product features | infrastructure
Required skills
Physical design (Planning, Place and route), Physical verification, Timing closure, Signal integrity analysis, Power/area/performance trade-off evaluation, IP integration (Broadcom IPs, memories, SerDes, I/O), Test structure integration, Clocking architecture design
Preferred skills
Experience with mission and test mode timing analysis
Technologies
CMOS, ASIC, SerDes, I/O subsystems
Responsibilities
Integrate Broadcom IPs, memories, SerDes, and I/O subsystems; Integrate test structures and clocking architectures; Evaluate design trade-offs involving power, area, and performance; Address challenges related to timing closure and signal integrity; Perform timing analysis for mission and test modes; Execute chip-level Planning, Place and route, physical verification, and tapeout
Seniority
Senior, hands-on IC