Physical Design Engineer
Core
Physical design and implementation of wafer-scale AI chips, focusing on synthesis, place and route, timing closure, and full-chip integration.
Role type
Senior IC physical design engineer (wafer-scale)
Builds
Wafer-scale AI chips for high-speed training and inference
Domain
Semiconductor / AI Hardware
Deliverable
production ML models
Required skills
Physical design (PD), timing closure, physical verification (PDV), IR/EM analysis, floor-planning, Tcl/Python scripting, RTL collaboration
Preferred skills
Complete physical design flow, Synopsys tool suite, Synthesis, Static Timing Analysis (STA)
Technologies
ICV, Calibre, Synopsys tool suite
Responsibilities
Perform synthesis, place and route, timing closure, and block/sign-off; collaborate with RTL teams on full-chip integration; resolve DRC and LVS issues; optimize for power/performance/area
Seniority
Senior, hands-on IC