Senior Digital Mixed-Signal (DMS) Verification Engineer
Core
Architect and maintain UVM-based testbenches for functional verification of complex mixed-signal ASIC products, acting as a methodology leader and technical bridge between US digital design teams and global verification teams.
Role type
Senior IC mixed-signal ASIC verification engineer
Builds
Mixed-signal ASIC IP for next-generation enterprise storage solutions
Domain
Semiconductor / Mixed-Signal ASIC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM/OVM, SystemVerilog Assertions (SVA), event-driven simulator-based modeling, coverage-driven verification, cross-site team coordination, analog/digital boundary understanding
Preferred skills
Behavioral modeling of analog circuits, scripting for verification workflow automation
Technologies
UVM, OVM, SystemVerilog, event-driven simulators
Responsibilities
Architect advanced UVM-based testbenches for mixed-signal ASICs; Champion verification quality by integrating new methodologies like SVA; Act as liaison between local US digital design teams and worldwide verification teams; Lead initiatives to integrate modern automation and AI-assisted verification workflows; Own verification efforts at block and system levels for major tape-out projects
Seniority
Senior, hands-on IC