Senior Serdes System Design Engineer/Architect
Core
Design, verify, and implement signal processing algorithms for high-speed Serdes physical layer products at 100G+ speeds.
Role type
Senior IC system design engineer (Serdes/Physical Layer)
Builds
High-speed Serdes ASICs and wireline communication standards
Domain
Semiconductor / High-speed communication / Physical Layer
Deliverable
production ML models | product features
Required skills
Communication theory, Digital signal processing, Analog circuit behavior, Transmission line theory, MATLAB, C/C++, Lab testing, CDR PLL design, Equalization techniques
Preferred skills
RTL coding, IEEE 802.3/OIF 100G/200G/400G Serdes standards, PCIe Gen6/Gen7 standards
Technologies
MATLAB, C/C++, RTL, IEEE 802.3, OIF, PCIe
Responsibilities
Develop channel models and run simulations to define Serdes architecture; Define and document signal processing block requirements, architecture, and lab test plan; Develop bit-exact MATLAB and C/C++ system models for simulation and verification; Develop and run system-level simulation suites to evaluate architectural tradeoffs; Perform vector matching verification with RTL simulations; Develop, test, and debug firmware associated with physical layer functionality; Lab testing and debug of Serdes; Documentation/application note development and customer support; Support marketing group with customer meetings and collateral
Seniority
Senior, hands-on IC