IC Package Design / Development
Core
Design and deliver next-generation IC package architecture, substrate design, and high-volume manufacturing execution for advanced node silicon (7nm, 5nm, 3nm).
Role type
Senior IC Packaging Engineer
Builds
Advanced packaging solutions for high-speed IO (224G/112G SerDes, PCIe Gen 6/7) and analog/digital IP/PHY products
Domain
Semiconductor manufacturing, advanced packaging, high-speed digital/analog design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
substrate design, floor-planning, bump architecture, SI/PI optimization, thermal management, high layer count BGA packaging, NPI execution, cross-functional leadership
Preferred skills
Electrical/Mechanical/Materials Science degree, global OSAT collaboration, Cadence Allegro APD/SIP proficiency
Technologies
Cadence Allegro APD/SIP, 7nm/5nm/3nm silicon nodes
Responsibilities
Optimize chip floorplan and IO architecture for advanced node products; Perform BGA substrate design ensuring SI/PI and thermal targets; Define assembly BOM, process flows, and design rules for advanced packaging; Drive NPI bring-up and HVM qualification with assembly and manufacturing partners; Resolve quality and reliability issues during high-volume manufacturing
Seniority
Senior, hands-on IC
