Silicon Design Methodology and Automation - RV
Core
Develop, enhance, and maintain scalable automation, flows, and methodologies for EMIR (Electromigration and IR Drop) analysis and signoff to ensure power integrity and reliability closure across advanced technology nodes and complex FPGA designs.
Role type
Reliability Verification Design Methodology and Automation Engineer
Builds
Scalable EMIR analysis flows, automation infrastructure, and standardized signoff methodologies for Altera silicon programs.
Domain
Semiconductor design, power integrity, and reliability verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
EMIR analysis, flow development, automation, Voltus, Redhawk-SC, Totem, Voltus-XFi, Python, Tcl, Perl, shell, power integrity fundamentals, EM, IR drop analysis, reliability closure, advanced technology nodes, signoff methodologies
Preferred skills
EMIR signoff criteria definition, full-chip power analysis, cross-tool correlation, thermal/package interaction knowledge, system-level reliability, AI/ML for analysis efficiency
Technologies
Voltus, Redhawk-SC, Totem, Voltus-XFi
Responsibilities
Develop and deploy state-of-the-art EMIR flows and methodologies; Own automation and infrastructure for EMIR analysis; Execute project-level EMIR signoff; Lead advanced-node project RV execution and signoff; Analyze EMIR violations and drive mitigation strategies; Provide technical guidance, documentation, and training on EMIR methodologies
Seniority
Senior, hands-on IC
