Analog/Mixed Signal Verilog Modeling Design Engineer
Core
Develop Digital-Mixed Signal (DMS) models of analog IPs (touch controller AFEs, wireless power charging, health sensing AFE, satellite AFEs) using SystemVerilog for chip verification.
Role type
Analog/Mixed Signal Verilog Modeling Design Engineer
Builds
DMS models for analog IPs used in chip verification
Domain
Semiconductor / Analog Mixed Signal Design
Deliverable
production ML models | product features
Required skills
SystemVerilog, Verilog-AMS, analog circuit design (LDOs, TIAs, SARADC, comparators), RTL design, testbench creation, scripting (TCL/Perl/Python), AI tools for model generation
Preferred skills
Experience with Cadence wreal or EEnet packages, familiarity with Cadence linting & simulation tools (ncsim, xrun, vcs), analog schematic editor usage
Technologies
SystemVerilog, Verilog-AMS, Cadence wreal, EEnet, ncsim, xrun, vcs, TCL, Perl, Python, Cursor, chipAgents
Responsibilities
Develop DMS models of analog IPs, interface with analog design and chip DV teams, create testbenches, run SV vs schematic verification
Seniority
Senior, hands-on IC