Staff DFT Design Engineer
Core
Define end-to-end DFT architecture and strategy for complex FPGA designs and platforms, driving implementation, sign-off, and post-silicon yield initiatives.
Role type
Staff DFT Design Engineer (FPGA/SOC)
Builds
Custom design blocks & PNR flows for FPGA and SOC platforms
Domain
Semiconductor hardware design (FPGA/SOC)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DFT methodology, architecture & design, Verilog/SystemVerilog, debugging, problem-solving, IEEE 1149.1/1687 standards, SpyGlassDFT tools
Preferred skills
Post-silicon debug, yield ramp, ATE platforms, DFT design verification, low-power DFT, scripting automation (Python/Tcl/Perl)
Technologies
SpyGlassDFT, Python, Tcl, Perl
Responsibilities
Define DFT architecture and strategy, drive DFT requirements at architecture/RTL stages, lead DFT implementation (Scan, ATPG, BIST, SSN), resolve testability/clocking challenges, partner on timing closure, lead post-silicon yield improvement, mentor engineers
Seniority
Staff, hands-on IC with significant leadership
