ML/AI Timing and Power Flow Expert
Core
Architect and optimize advanced ASIC/FPGA implementation flows, focusing on timing and power convergence across full-chip and block-level designs using ML/AI to enhance predictability and automate bottleneck analysis.
Role type
Senior IC EDA flow expert (timing/power/library)
Builds
Scalable, automated flow infrastructure for timing, power, and library characterization
Domain
Semiconductor / EDA / ASIC & FPGA design
Deliverable
production ML models | product features
Required skills
STA flow development, UPF integration, library generation and characterization, timing analysis, power analysis, Python/Tcl/Perl coding, flow automation, anomaly detection, data-driven trend analysis
Preferred skills
Advanced-node SoC design support, ML/AI frameworks for EDA, deep data analytics, end-to-end methodology enhancement, cross-functional collaboration
Technologies
Tcl, Python, Perl, UPF, STA tools, power analysis tools
Responsibilities
Develop and maintain robust timing and power flows across the physical design lifecycle; Own and drive STA flows including setup, analysis, and collateral generation; Design and implement power-aware flows with UPF integration; Lead standard-cell and macro library generation and characterization; Build and maintain scalable, automated flow infrastructure; Apply ML/AI-driven approaches to accelerate flow development and improve debug efficiency; Generate and review timing, power, and library reports; Debug complex timing, power, library, and flow issues across multiple design stages.
Seniority
Senior, hands-on IC