Digital Verification Intern
Core
Creating digital verification environments, writing testcases, and debugging mixed-signal ICs for power management and signal management functions.
Role type
Digital Verification Engineer Intern
Builds
Digital and mixed-signal ICs for power management and signal management
Domain
Semiconductor / Integrated Power Semiconductors
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, RTL coding, test plan generation, gate-level verification, TCL scripting, Python, C/C++
Preferred skills
SCAN and DFT techniques, power management industry knowledge, I2C/I3C/SPI/USB/PMBUS protocols
Technologies
UVM, SystemVerilog, TCL, Python, C/C++
Responsibilities
Create Digital Verification environments with UVM and SystemVerilog, Write Digital and Mixed-Signal testcases and assertions/checkers, Analyze and debug test results, code coverage and functional coverage, Support on Verification IPs and standard tests, environments, checkers, etc., Assist with Test Plan generation based on design requirements and product datasheets, Close interaction with Senior Digital Design, Digital Verification and Analog Design Engineers to develop System Level and Behavioral Models, Automation and scripting, Gate-Level verification
Seniority
Intern