Senior Staff Verification Engineer For Worldguard
Core
Senior verification engineer responsible for planning, developing, and closing verification coverage for RISC-V processor architectures.
Role type
Senior Staff Verification Engineer (CPU/RISC-V)
Builds
RISC-V processor IP and compute platforms
Domain
Semiconductor / Chip Design / RISC-V Architecture
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, constrained-random verification, RTL debugging, coverage closure, C programming, RISC-V architecture knowledge, security architecture knowledge, object-oriented programming, bus interface knowledge (AXI, AHB, PCIe), third-party VIP integration, CPU micro-architecture knowledge
Preferred skills
Python/Perl scripting, OVM or VMM methodologies, x86 or ARM architecture knowledge
Technologies
SystemVerilog, UVM, Verdi, SimVision, Python, Perl, C, C++, AXI, AHB, PCIe
Responsibilities
Analyze architectural specifications to define verification strategies and create comprehensive test plans; Design and implement scalable, reusable, and constrained-random verification environments; Write complex sequences and constrained-random tests to stress-test the IP; Perform deep-dive root cause analysis on RTL design failures and testbench issues; Define and track functional and code coverage metrics using cover groups and cover points.
Seniority
Senior Staff, hands-on IC
