Sr Engineer, Low Power Verification & Formal Equivalence
Core
Drive low power verification signoff and formal equivalence checks for advanced high-performance design blocks and sub-systems in the RTL-to-GDSII flow.
Role type
Senior IC verification engineer (low power & formal)
Builds
Static low power verification flows, UPF implementations, and logical equivalence checking (LEC) for chip design blocks.
Domain
Semiconductor / ASIC / SoC / Low Power Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UPF coding and debugging, static low power verification (RTL and post-PNR), Logical Equivalence Checking (LEC), formal ECO flows, Power Management library cells (ISO, LS, AON, Retention), ASIC/SoC design verification
Preferred skills
Backend Physical Design flow knowledge, scripting automation (Tcl, Python, Perl)
Technologies
Synopsys VC Low Power (VCLP), Synopsys Formality, UPF
Responsibilities
Execute static low power verification checks to ensure zero structural bugs; Deploy and optimize UPF coding and verification flows; Own and drive the Logical Equivalence Checking (LEC) flow from RTL to post-route netlists; Debug power intent violations and provide optimal UPF and equivalence solutions alongside backend teams.
Seniority
Senior, hands-on IC
