Senior Engineer, R2G Methodology and PD execution
Core
Execute and optimize RTL-to-GDS implementation flow for high-performance CPU cores on leading-edge process nodes.
Role type
Senior Physical Design Engineer (Methodology & Execution)
Builds
High-performance CPU cores for data-intensive applications
Domain
Semiconductor / Chip Design / Physical Design
Deliverable
production ML models | product features
Required skills
RTL-to-GDS flow execution, block-level implementation ownership, PPA optimization (timing-driven placement, CTS, routing), ML-enhanced design space exploration, Tcl/Python scripting, FinFET node knowledge (N5/N3), Synopsys Fusion Compiler expertise
Preferred skills
N2/GAAFET node familiarity, hierarchical closure experience, SRAM/Std Cell IP collaboration
Technologies
Synopsys Fusion Compiler, ICC2, PrimeTime, StarRC, DSO.ai
Responsibilities
Implement and validate production-ready RTL-to-GDS recipes; drive end-to-end implementation of medium-sized CPU sub-blocks; optimize block-level PPA using advanced timing and routing techniques; utilize ML tools for design space exploration; debug flow and tool-related issues; develop Tcl/Python scripts for flow automation
Seniority
Senior, hands-on IC