NoC Design Verification Engineer
Core
Develop and execute verification plans for NoC and coherent interconnect IP/subsystems to ensure correct on-chip communication and data movement.
Role type
Senior IC design verification engineer (NoC/interconnect)
Builds
Verification environments, testbenches, checkers, scoreboards, and assertions for NoC and SoC interconnects
Domain
Semiconductor chip design, on-chip interconnects, computer architecture
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, constrained-random verification, assertions (SVA), functional coverage, RTL debugging, computer architecture knowledge
Preferred skills
NoC fabric verification, VIP development, Python/Perl scripting, formal verification, cache coherency understanding
Technologies
SystemVerilog, UVM, SVA, Python, Perl, shell
Responsibilities
Develop and execute verification plans for NoC and coherent interconnect IP/subsystems; Build UVM/SystemVerilog-based verification environments, testbenches, checkers, scoreboards, assertions, and functional coverage; Verify multiple NoC configurations, topologies, routing scenarios, and protocol interactions; Create assertions, checkers, and coverage aligned with evolving NoCLink specifications and configuration requirements; Drive verification for subsystem integration involving memory fabrics, cache/coherency paths, and large SoC interconnects; Debug simulation failures, isolate root cause, and work with RTL/design teams on closure
Seniority
Senior, hands-on IC
