Senior Verification Engineer
Core
Drive verification of cache and memory-subsystem functionality, focusing on cache coherency, ordering, correctness, and subsystem integration for RISC-V compute platforms.
Role type
Senior IC design verification engineer
Builds
RISC-V processor cores and memory subsystems for high-performance compute applications
Domain
Semiconductor chip design, computer architecture, memory systems
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, computer architecture, cache coherency concepts, test plan creation, testbench development, assertion writing, coverage analysis, complex debugging
Preferred skills
Multicore system verification, subsystem integration, Python scripting, formal verification, emulation/FPGA-assisted debug
Technologies
SystemVerilog, UVM, Python, FPGA, Emulation tools
Responsibilities
Create verification strategies and test plans for cache and memory subsystems; Develop and maintain verification environments, checkers, scoreboards, and assertions; Execute directed and constrained-random tests to expose corner cases; Analyze failures and drive fixes across RTL and testbench infrastructure; Collaborate with architecture and design teams to clarify requirements; Write functional coverage and close coverage holes to ensure signoff quality
Seniority
Senior, hands-on IC
