Senior Engineer, Physical Design - Interconnects
Core
Senior Physical Design Engineer responsible for RTL-to-GDSII implementation of high-speed System IP components including Network-on-Chips (NoC), coherent CPU clusters, and Uncore subsystems.
Role type
Senior IC physical design engineer (interconnects)
Builds
High-performance SoC interconnects and subsystems for RISC-V compute platforms
Domain
Semiconductor chip design, RISC-V architecture, high-speed digital logic
Deliverable
production ML models | product features
Required skills
Physical design implementation, hierarchical design techniques, timing closure (MMMC), PPA optimization, RTL reading, EDA tool proficiency
Preferred skills
Experience with FinFET nodes (7nm or below), microarchitectural optimization, automated design flows
Technologies
Synopsys, Cadence
Responsibilities
Own end-to-end RTL-to-GDSII implementation of complex System IP; Partner with architecture to resolve physical bottlenecks; Develop system-level floorplans for bus-heavy subsystems; Solve high-frequency timing and clock distribution challenges; Execute and improve automated synthesis, place-and-route, and sign-off flows
Seniority
Senior, hands-on IC
