Senior Staff Engineer, Static Timing Analysis (STA) Lead
Core
Primary technical authority and owner for timing-related aspects of next-generation, high-speed data center scale CPUs, defining sign-off criteria and driving advanced timing methodologies.
Role type
Senior Staff Engineer, Static Timing Analysis (STA) Lead
Builds
High-performance compute architectures at cutting-edge process nodes (N3/N2)
Domain
Semiconductor chip design, VLSI, Data Center CPUs
Deliverable
production ML models | product features | infrastructure
Required skills
Timing Signoff process expertise, Synopsys PrimeTime, 3nm (N3) process node experience, Physical Design Flow (Synthesis, Place and Route), SDC development and debugging, Clock Tree Synthesis (CTS) architectures
Preferred skills
Data center scale CPU timing closure, 2nm (N2) technology nodes, Synopsys FusionCompiler, Machine Learning-based timing prediction
Technologies
Synopsys PrimeTime, Synopsys FusionCompiler
Responsibilities
Define sign-off criteria and margins, develop and deploy correct-by-construction methodologies, architect and maintain advanced tracking platforms for timing convergence metrics, lead SDC quality assurance
Seniority
Senior Staff, hands-on IC technical leadership
