Senior RTL Design Engineer - Cache Subsystem
Core
Architect, design, and implement high-performance cache subsystems for RISC-V CPU cores, optimizing for frequency, area, and power.
Role type
Senior IC microarchitect and RTL design engineer (cache subsystem)
Builds
High-performance CPU cores and cache subsystems based on RISC-V architecture
Domain
Semiconductor / CPU Design / RISC-V
Deliverable
production ML models | product features
Required skills
Cache subsystem architecture, Multi-level coherent cache design, TileLink/interconnect architecture, RTL design (Verilog/System Verilog/VHDL), Microarchitecture specification, Physical design optimization, Performance modeling
Preferred skills
RISC-V architecture, Scala/Chisel, UVM/Formal verification, Object-oriented/functional programming
Technologies
Verilog, System Verilog, VHDL, TileLink, RISC-V, Scala, Chisel, UVM
Responsibilities
Architect and implement new high-performance cache subsystems in CPU core generators, Develop microarchitecture specifications and documentation, Execute sandbox verification and collaborate on verification test plans, Collaborate with physical implementation teams to meet frequency/area/power goals, Work with performance modeling teams for optimization
Seniority
Senior, hands-on IC
