Sr. Engineer, Performance Infrastructure
Core
Driving performance analysis, correlation, and verification for a high-performance RISC-V CPU design.
Role type
Senior IC performance infrastructure engineer (CPU design)
Builds
High-performance RISC-V CPU cores
Domain
Semiconductor / CPU Design / AI Infrastructure
Deliverable
production ML models | product features | infrastructure
Required skills
C++, Python, RTL debugging, microarchitecture knowledge, performance verification, tool development
Preferred skills
Infrastructure methodology, power/performance/area optimization
Technologies
RISC-V, RTL, simulation and emulation tools
Responsibilities
Verify performance and correlate with RTL, enhance design environment and tools, collaborate with RTL engineers and architects, optimize power, performance, and area
Seniority
Senior, hands-on IC
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