Stage Ingénieur : Vérification d’architectures d’interconnexion pour SoC automobiles (F/H)
Core
Study and validate complex interconnect architectures (buses, crossbars, NoC) and infrastructure blocks for next-generation automotive System-on-Chip (SoC) devices.
Role type
Final-year engineering student (IC verification engineer)
Builds
Functional verification environments and reference models for automotive SoC interconnects
Domain
Automotive electronics / Digital SoC design
Required skills
Digital architecture, RTL design, Embedded communication protocols (APB, AHB, AXI), SystemVerilog, UVM, Formal verification, Simulation analysis
Preferred skills
Experience with memory arbiters, address routers, protocol bridges, Multi-master interconnect elements
Technologies
SystemVerilog, UVM, APB, AHB, AXI, NoC
Responsibilities
Study SoC interconnect architectures (shared buses, crossbars, NoC), Analyze performance requirements (latency, bandwidth, scalability), Develop reference models and verification components, Implement verification environments, Define test scenarios for memory contention and QoS, Apply formal verification techniques, Analyze simulation results and functional coverage (via careerplan.io/jobs/R-10067015-stage-ingenieur-verification-darchitectures-dinterconnexion-pour-soc-automobiles-fh-at-nxp)
Seniority
Intern (Final-year student)
