Stage Ingénieur : Génération de VIP et d’assertions pour IP mixtes par agents IA (F/H)
Core
Develop an AI agent to automate the generation of reusable verification components (VIPs, checkers, assertions) for digitally controlled mixed-signal IPs, specifically DC/DC converters.
Role type
Intern, AI-assisted verification flow development
Builds
Reusable SystemVerilog/UVM verification templates and AI-driven generation pipelines
Domain
Semiconductor verification, mixed-signal ICs, digital control loops
Deliverable
production ML models
Required skills
SystemVerilog, UVM, Python, AI agents, technical specification analysis, simulation environments
Preferred skills
Generative AI, code generation automation, DC/DC converter architecture knowledge
Technologies
SystemVerilog, UVM, Python, AI agents
Responsibilities
Analyze functional specifications to extract verifiable requirements; Design methodology for automatic VIP generation; Implement AI agent for specification analysis; Generate SystemVerilog assertions and UVM templates; Integrate and validate generated components in simulation; Document solution architecture and results
Seniority
Intern
