Stage Ingénieur : Génération de VIP et d’assertions pour IP mixtes par agents IA (F/H)
Core
Develop an AI agent to automate the generation of reusable verification components (VIPs, checkers, assertions) for digitally controlled mixed-signal IPs, specifically DC/DC converters.
Role type
Research & Development Intern (AI for Verification)
Builds
AI-driven verification flows and SystemVerilog/UVM templates for mixed-signal IP validation
Domain
Semiconductor verification, Mixed-signal ICs, Generative AI
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, Digital Design, Python, Functional Specification Analysis
Preferred skills
Generative AI, AI Agents, DC/DC Converter Architecture
Technologies
SystemVerilog, UVM, Python, AI Agents
Responsibilities
Analyze functional specifications to extract verifiable requirements; Design methodology for automatic VIP generation; Implement AI agent for specification analysis; Generate SystemVerilog/UVM templates and assertions; Integrate and validate generated components in simulation environment.
Seniority
Intern